ADSP-21062L Datasheet

• 40MHz (25ns instruction rate) SISD SHARC Core
• 120MFLOPs peak performance
• Code compatible with all SHARC processors
• Supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math
• 2Mbits of on-chip dual-ported SRAM
• Glueless connection for scalable DSP multiprocessing
• Six Link Ports for point to point connectivity and array multiprocessing
• Two synchronous serial ports with independent transmit and receive functions
• 10 Channel DMA controller
• Host Processor Interface

The ADSP-21062L SHARC DSPs are signal processing microcomputers that offer new capabilities and levels of performance. The ADSP-2106L SHARCs are 32-bit processors optimized for high performance DSP applications. The ADSP-21062L builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dual-ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.

Fabricated in a high speed, low power CMOS process, the ADSP-21062L has a 25 ns instruction cycle time and operates at 40 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle.

The ADSP-21062L SHARC DSP represents a new standard of integration for signal computers, combining a high performance floating-point DSP core with integrated, on-chip system features including a 4 Mbit SRAM memory (2 Mbit on the ADSP-21062), host processor interface, DMA controller, serial ports, and link port and parallel bus connectivity for glueless DSP multiprocessing.