ADSP-21061L Datasheet

• 50MHz (20ns instruction rate) SISD SHARC Core
• 150MFLOPs peak performance
• Code compatible with all SHARC processors
• Supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math
• 1Mbit of on-chip dual-ported SRAM
• Glueless connection for scalable DSP multiprocessing
• Two synchronous serial ports with independent transmit and receive functions
• 6 Channel DMA controller
• Host Processor Interface

The ADSP-21061L is the newest member of the powerful SHARC^® family of floating point processors. The SHARC^® are signal processing microcomputers that offer new capabilities and levels of integration and performance. The ADSP-21061L is the low power (3.3 volt) version of the ADSP-21061. The ADSP-21061L is a 32-bit processor optimized for high performance DSP applications. The ADSP-21061L combines the ADSP-21000 DSP core with a dual-ported on-chip SRAM and an I/O processor with a dedicated I/O bus to form a complete system-in-a-chip.

Fabricated in a high-speed, low-power CMOS process, the ADSP-21061L has a 25 ns instruction cycle time operating at 40 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle.

The ADSP-21061L SHARC combines a high-performance floating-point DSP core with integrated, on-chip system features, including a 1 Mbit SRAM memory, host processor interface, DMA controller, serial ports and parallel bus connectivity for glueless DSP multiprocessing.