ADF4401A Datasheet

• RF output frequency range: 62.5 MHz to 8000 MHz
• 9 fs rms jitter at 8 GHz output
• 17 dBm IF output power at 6 GHz RF output
• 90 dBc LO_IN to RF output
• 90 dBc spurious-free dynamic range
• Low phase noise, voltage controlled oscillator
• Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
• 3.3 V analog, digital, and mixer power supplies
• 5 V amplifier and VCO power supply
• RF output mute function
• 18.00 mm × 18.00 mm, 80-terminal LGA_CAV
• Supported in the ADIsimPLL design tool

• Instrumentation and measurement
• Automated test equipment
• Aerospace and defense

The ADF4401A is a fully integrated, system in package (SiP) translation loop (also known as an offset loop) module that includes a voltage controlled oscillator (VCO) and calibration phase-locked loop (PLL) circuit. Designed for highly jitter sensitive applications, this solution reduces board space and complexity compared to traditional discrete translation loop solutions designed on a printed circuit board (PCB). The time to market is significantly reduced by taking advantage of this highly integrated solution with in package circuitry and enhanced isolation that attenuates spurious components. The ADF4401A provides a frequency synthesis solution for engineers designing highly competitive systems.

The ADF4401A requires an external phase detector or phase frequency detector (PFD) and an external local oscillator (LO) to form a frequency synthesis solution.

The ADF4401A implements an integrated downconversion mixing stage in the feedback loop that sets the loop gain to 1 and minimizes the in band phase noise. By combining the frequency downconversion stage and low noise, integrated, wideband, VCO technology from Analog Devices, Inc., the ADF4401A offers a wideband jitter performance of 9 fs rms at 8 GHz output. The output jitter performance is largely dependent on the performance of the external offset LO.

The ADF4401A module uses an internal PFD and VCO calibration circuitry to select the appropriate VCO band. The user can disable the calibration circuitry and close the loop using the external PFD. All on-chip registers are controlled via a serial port interface (SPI).