ADF4382 Datasheet

• Output frequency range: 687.5 MHz to 22 GHz
• Integrated RMS jitter at 20 GHz = 20 fs (integration bandwidth: 100 Hz to 100 MHz)
• Integrated RMS jitter at 20 GHz = 31 fs (ADC SNR method)
• VCO fast calibration time < 1 μs
• VCO autocalibration time < 100μs
• Phase noise floor: −156 dBc/Hz at 20 GHz
• PLL Specifications:
  • -239 dBc/Hz: Normalized In-Band Phase Noise Floor
  • -287 dBc/Hz: Normalized In-Band 1/f Noise
• • 625 MHz maximum phase/frequency detector input frequency
  • 4.5 GHz reference input frequency
  • Typical spurious f_PFD: −90 dBc
• Reference to output delay specifications
  • Propagation delay temperature coefficient: 0.06 ps/°C
  • Adjustment step size: <1 ps
• Multichip output phase alignment
• 3.3 V and 5 V power supplies
• ADIsimPLL™ loop filter design tool support
• 7 mm × 7 mm, 48-terminal LGA
• −40°C to +105°C operating temperature

• High Performance Data Converter Clocking
• Wireless infrastructure (MC-GSM, 5G, 6G)
• Test and Measurement

The ADF4382 is a high performance, ultra-low jitter, fractional-N phased-locked loop (PLL) with an integrated voltage controlled oscillator (VCO) ideally suited for local oscillator (LO) generation for 5G applications or data converter clock applications. The high performance PLL has a figure of merit of −239 dBc/Hz, low 1/f noise and high PFD frequency of 625 MHz in integer mode that can achieve ultra-low in-band noise and integrated jitter. The ADF4382 can generate frequencies in a fundamental octave range of 11 GHz to 22 GHz, thereby eliminating the need for subharmonic filters. The output dividers on the ADF4382 allow a complete output frequency range to be generated from 687.5 MHz to 22 GHz.

For multiple data converter clock applications, the ADF4382 automatically aligns its output to the input reference edge by including the output divider in the PLL feedback loop. For applications that require deterministic delay or delay adjustment capability, a programmable reference to output delay with <1 ps resolution is provided. The reference to output delay matching across multiple devices and over temperature allows predictable and precise multichip alignment.

The simplicity of the ADF4382 block diagram eases development time with a simplified serial peripheral interface (SPI) register map, external SYNC input, and repeatable multichip alignment in both integer and fractional mode.