ADAU1361 Datasheet

• 24-bit stereo audio ADC and DAC: >98 dB SNR
• Sampling rates from 8 kHz to 96 kHz
• Low power: 7 mW record, 7 mW playback, 48 kHz at 1.8 V
• 6 analog input pins, configurable for single-ended or differential inputs
• Flexible analog input/output mixers
• Stereo digital microphone input
• Analog outputs: 2 differential stereo, 2 single-ended stereo, 1 mono headphone driver output
• PLL supporting input clocks from 8 MHz to 27 MHz
• Analog automatic level control (ALC)
• Microphone bias reference voltage
• Analog and digital I/O: 1.8 V to 3.65 V
• I²C and SPI control interfaces
• Digital audio serial data I/O: stereo and time-division multiplexing (TDM) modes
• Software-controllable clickless mute
• Software power-down
• 32-lead, 5 mm × 5 mm LFCSP
• −40°C to +85°C operating temperature range

• Smartphones/Multimedia phones
• Digital Still Cameras/Digital Video Cameras
• Portable Media Players/Portable Audio Players
• Phone accessories products

The ADAU1361 is a low power, stereo audio codec that supports stereo 48 kHz record and playback at 14 mW from a 1.8 V analog supply. The stereo audio ADCs and DACs support sample rates from 8 kHz to 96 kHz as well as a digital volume control. The ADAU1361 is ideal for battery-powered audio and telephony applications.

The record path includes an integrated microphone bias circuit and six inputs. The inputs can be mixed and muxed before the ADC, or they can be configured to bypass the ADC. The ADAU1361 includes a stereo digital microphone input.

The ADAU1361 includes five high power output drivers (two differential and three single-ended), supporting stereo headphones, an earpiece, or other output transducer. AC-coupled or capless configurations are supported. Individual fine level controls are supported on all analog outputs. The output mixer stage allows for flexible routing of audio.

The serial control bus supports the I²C and SPI protocols. The serial audio bus is programmable for I²S, left-/right-justified, and TDM modes. A programmable PLL supports flexible clock generation for all standard integer rates and fractional master clocks from 8 MHz to 27 MHz.