AD9789 Datasheet

• DOCSIS 3.0 performance: 4 QAM carriers
  • ACLR over full band (47 MHz to 1 GHz)
    • −75 dBc @ f_OUT = 200 MHz
    • −72 dBc @ f_OUT = 800 MHz (noise)
    • −67 dBc @ f_OUT = 800 MHz (harmonics)
  • Unequalized MER = 42 dB
• On chip and bypassable
  • 4 QAM encoders with SRRC filters, 16× to 512× interpolation, rate converters, and modulators
• Flexible data interface: 4, 8, 16, or 32 bits wide with parity
• Power: 1.6 W (I_FS = 20 mA, f_DAC = 2.4 GHz, LVDS interface)
• Direct to RF synthesis support with f_S mix mode
• Built-in self-test (BIST) support
  • Input connectivity check
  • Internal random number generator

• Broadband communications systems
• CMTS/DVB
• Cellular infrastructure
• Point-to-point wireless

The AD9789 is a flexible QAM encoder/interpolator/upconverter combined with a high performance, 2400 MSPS, 14-bit RF digital-to-analog converter (DAC). The flexible digital interface can accept up to four channels of complex data. The QAM encoder supports constellation sizes of 16, 32, 64, 128, and 256 with SRRC filter coefficients for all standards.

The on-chip rate converter supports a wide range of baud rates with a fixed DAC clock. The digital upconverter can place the channels from 0 to 0.5 × f_DAC. This permits four contiguous channels to be synthesized and placed anywhere from dc to f_DAC.

The AD9789 includes a serial peripheral interface (SPI) for device configuration and status register readback. The flexible digital interface can be configured for data bus widths of 4, 8, 16, and 32 bits. It can accept real or complex data.

The AD9789 operates from 1.5 V, 1.8 V, and 3.3 V supplies for a total power consumption of 1.6 W. It is supplied in a 164-ball chip scale package ball grid array for lower thermal impedance and reduced package parasitics. No special power sequencing is required. The clock receiver powers up muted to prevent start-up noise.