AD9559 Datasheet

• Supports GR-1244 Stratum 3 stability in holdover mode
• Supports smooth reference switchover with virtually no disturbance on output phase
• Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems
• Supports ITU-T G.8262 synchronous Ethernet node clocks
• Supports ITU-T G.823, G.824, G.825, and G.8261
• Auto/manual holdover and reference switchover
• Adaptive clocking allows dynamic adjustment of feedback dividers for use in OTN mapping/demapping applications
• Dual digital PLL architecture with four reference inputs (single-ended or differential)
• 4x2 crosspoint allows any reference input to drive either PLL
• Input reference frequencies from 2 kHz to 1250 MHz
• Reference validation and frequency monitoring (2 ppm)
• Programmable input reference switchover priority
• 20-bit programmable input reference divider
• 4 pairs of clock output pins with each pair configurable as a single differential LVDS/HSTL output or as 2 single-ended CMOS outputs
• Output frequencies: 262 kHz to 1250 MHz
• Programmable 17-bit integer and 23-bit fractional feedback divider in digital PLL
• Programmable digital loop filter covering loop bandwidths from 0.1 Hz to 2 kHz
• Low noise system clock multiplier
• Optional crystal resonator for system clock input
• On-chip EEPROM to store multiple power-up profiles
• Pin program function for easy frequency translation configuration
• Software controlled power-down
• 72-lead (10 mm × 10 mm) LFCSP package

• Network synchronization, including Synchronous Ethernet and OTN mapping/de-mapping
• Cleanup of reference clock jitter
• SONET/SDH clocks up to OC-192, including FEC
• Stratum 3 holdover, jitter cleanup, and phase transient control
• Wireless base station controllers
• Cable infrastructure
• Data communications

The AD9559 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9559 generates an output clock synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9559 continuously generates a low jitter output clock even when all reference inputs have failed.

The AD9559 operates over an industrial temperature range of −40°C to +85°C. If a single DPLL version of this part is needed, refer to the AD9557.