AD9515 Datasheet

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

Part No.:
AD9515
Manufacturer:
Analog Devices, Inc.
Page:
28 Pages
Size:
353 KB
Views:
0
Update Time:
2025-07-02 12:44:26

AD9515 DataSheet Applicable Part

Part No. In Stock Price Packaging SPQ Marking MSL Pins Temp Range Package Description
AD9515BCPZ 0 $7.407 Tray 490 AD9515BCPZ 3 32 -40°C ~ 85°C 32-Lead LFCSP
AD9515BCPZ-REEL7 0 $7.407 Reel 1500 AD9515BCPZ 3 32 -40°C ~ 85°C 32-Lead LFCSP
SPQ:Standard Pack Quantity;MSL:Moisture Sensitivity Level

AD9515 DataSheet PDF

AD9515 Features

  • 1.6 GHz differential clock input
  • 2 programmable dividers
    Divide-by in range from 1 to 32
    Phase select for coarse delay adjust
  • 1.6 GHz LVPECL clock output
    Additive output jitter 225 fs rms
  • 800 MHz/250 MHz LVDS/CMOS clock output
    Additive output jitter 300 fs rms/290 fs rms
    Time delays up to 10 ns
  • Device configured with 4-level logic pins
  • Space-saving, 32-lead LFCSP

AD9515 Applications

  • Low jitter, low phase noise clock distribution
  • Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
  • High performance wireless transceivers
  • High performance instrumentation
  • Broadband infrastructure
  • ATE

AD9515 Description

The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

There are two independent clock outputs. One output is LVPECL, while the other output can be set to either LVDS or CMOS levels. The LVPECL output operates to 1.6 GHz. The other output operates to 800 MHz in LVDS mode and to 250 MHz in CMOS mode.

Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to the other clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment.

The LVDS/CMOS output features a delay element with three selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each with 16 steps of fine adjustment.

The AD9515 does not require an external controller for operation or setup. The device is programmed by means of 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to ⅓ VS. The VREF pin provides a level of ⅔ VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.

The AD9515 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter.

The AD9515 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. The temperature range is −40°C to +85°C.

AD9515 Datasheet FAQs