AD9218 Datasheet

10-Bit, 40/65/80/105 MSPS 3 V Dual Analog-to-Digital Converter

Part No.:
AD9218
Manufacturer:
Analog Devices, Inc.
Page:
24 Pages
Size:
2052 KB
Views:
0
Update Time:
2025-10-24 10:33:54

AD9218 DataSheet Applicable Part

Part No. In Stock Price Packaging SPQ Marking MSL Pins Temp Range Package Description
SPQ:Standard Pack Quantity;MSL:Moisture Sensitivity Level

AD9218 DataSheet PDF

AD9218 Features

  • Dual 10-bit, 40 MSPS, 65 MSPS, 80 MSPS, and 105 MSPS ADC
  • Low power: 275 mW at 105 MSPS per channel
  • On-chip reference and track-and-hold
  • 300 MHz analog bandwidth each channel
  • SNR = 57 dB @ 41 MHz, Encode = 80 MSPS
  • 1 V p-p or 2 V p-p analog input range each channel
  • 3.0 V single-supply operation (2.7 V to 3.6 V)
  • Power-down mode for single-channel operation
  • Twos complement or offset binary output mode
  • Output data alignment mode
  • Pin compatible with the 8-bit AD9288
  • –75 dBc crosstalk between channels

AD9218 Applications

  • Battery-powered instruments
  • Hand-held scopemeters
  • Low cost digital oscilloscopes
  • I and Q communications
  • Ultrasound equipment

AD9218 Description

The AD9218 is a dual 10-bit monolithic sampling analog-to-digital converter with on-chip track-and-hold circuits. The product is low cost, low power, and is small and easy to use. The AD9218 operates at a 105 MSPS conversion rate with outstanding dynamic performance over its full operating range. Each channel can be operated independently.

The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power supply and a clock for full operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS compatible and a separate output power supply pin supports interfacing with 3.3 V or 2.5 V logic.

The clock input is TTL/CMOS compatible and the 10-bit digital outputs can be operated from 3.0 V (2.5 V to 3.6 V) supplies. User-selectable options offer a combination of power-down modes, digital data formats, and digital data timing schemes. In power-down mode, the digital outputs are driven to a high impedance state.

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