AD4005 Datasheet

• Easy Drive
  • Greatly reduced input kickback
    • Input current reduced to 0.5 μA/MSPS
  • Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS
  • First conversion accurate, no latency or pipeline delay
  • Input span compression for single-supply operation
  • Fast conversion allows low SPI clock rates
  • Input overvoltage clamp protection sinks up to 50 mA
  • SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface
• High performance
  • Differential analog input range: ±V_REF, V_REF from 2.4 V to 5.1 V
  • Throughput: 2 MSPS/1 MSPS options
  • INL: ±0.4 LSB maximum
  • Guaranteed 16-bit, no missing codes
• • SNR: 96.2 dB at f_IN = 1 kHz, V_REF = 5 V
  • THD: −123 dB at f_IN = 1 kHz, −99 dB at f_IN = 100 kHz
  • SINAD: 88.5 dB at f_IN = 1 MHz (see Figure 17 in data sheet)
  • Oversampled dynamic range
    • 99.3 dB for OSR = 2
    • 126 dB for OSR = 1024
• Low power
  • Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
  • 4.9 mW at 1 MSPS (VDD only)
  • 80 μW at 10 kSPS, 16 mW at 2 MSPS (total power)
• 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP
  • Pin compatible with AD4003/AD4007/AD4011 family
• Guaranteed operation: −40°C to +125°C

• Automated test equipment
• Machine automation
• Medical equipment
• Battery-powered equipment
• Precision data acquisition systems
• Instrumentation and control systems

The AD4005 are high accuracy, high speed, low power, 16-bit, Easy Drive, precision successive approximation register (SAR) analog-to-digital converters (ADCs) that operate from a single power supply, VDD. The reference voltage, V_REF, is applied externally and can be set independent of the supply voltage. The AD4005 power scales linearly with throughput.

Easy Drive features reduce both signal chain complexity and power consumption while enabling higher channel density. The reduced input current, particularly in high-Z mode, coupled with a long signal acquisition phase, eliminates the need for a dedicated ADC driver. Easy Drive broadens the range of companion circuitry that is capable of driving these ADCs (see Figure 2 in the data sheet).

Input span compression eliminates the need to provide a negative supply to the ADC driver amplifier while preserving access to the full ADC code range. The input overvoltage clamp protects the ADC inputs against overvoltage events, minimizing disturbances on the reference pin and eliminating the need for external protection diodes.

Fast device throughput up to 2 MSPS allows users to accurately capture high frequency signals and to implement oversampling techniques to alleviate the challenges associated with antialias filter designs. Decreased serial peripheral interface (SPI) clock rate requirements reduce digital input and output power consumption, broadens digital host options, and simplifies the task of sending data across digital isolation. The SPI-compatible serial user interface is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic by using the separate VIO logic supply.