MAX3100 Datasheet

SPI/MICROWIRE-Compatible UART in QSOP-16

Part No.:
MAX3100
Manufacturer:
Maxim Integrated
Page:
24 Pages
Size:
616 KB
Views:
0
Update Time:
2025-09-12 10:14:25

MAX3100 DataSheet Applicable Part

Part No. In Stock Price Packaging SPQ Marking MSL Pins Temp Range Package Description
SPQ:Standard Pack Quantity;MSL:Moisture Sensitivity Level

MAX3100 DataSheet PDF

MAX3100 Features

  • Small TQFN and QSOP Packages Available
  • Full-Featured UART:
    • IrDA SIR Timing Compatible
    • 8-Word FIFO Minimizes Processor Overhead at High Data Rates
    • Up to 230k Baud with a 3.6864MHz Crystal
    • 9-Bit Address-Recognition Interrupt
    • Receive Activity Interrupt in Shutdown
  • SPI/MICROWIRE-Compatible µC Interface
  • Lowest Power:
    • 150µA Operating Current at 3.3V
    • 10µA in Shutdown with Receive Interrupt
  • +2.7V to +5.5V Supply Voltage in Operating Mode
  • Schmitt-Trigger Inputs for Opto-Couplers
  • TX and RTS Outputs Sink 25mA for Opto-Couplers

MAX3100 Applications

  • Handheld Instruments (PDAs, Palmtops)
  • Intelligent Instruments
  • Isolated RS-232/RS-485: Directly Drives Optocouplers
  • Low-Cost IR Data Links for Computers/Peripherals
  • Small Networks in HVAC or Building Control
  • UART in SPI Systems

MAX3100 Description

The MAX3100 universal asynchronous receiver transmitter (UART) is the first UART specifically optimized for small microcontroller-based systems. Using an SPI™/MICROWIRE™ interface for communication with the host microcontroller (µC), the MAX3100 comes in a compact 24-pin-TQFN and 16-pin QSOP. The asynchronous I/O is suitable for use in RS-232, RS-485, IR, and opto-isolated data links. IR-link communication is easy with the MAX3100's infrared data association (IrDA) timing mode.

The MAX3100 includes a crystal oscillator and a baud-rate generator with software-programmable divider ratios for all common baud rates from 300 baud to 230k baud. A software- or hardware-invoked shutdown lowers quiescent current to 10µA, while allowing the MAX3100 to detect receiver activity.

An 8-word-deep first-in/first-out (FIFO) buffer minimizes processor overhead. This device also includes a flexible interrupt with four maskable sources, including address recognition on 9-bit networks. Two hardware-handshaking control lines are included (one input and one output).

The MAX3100 is available in 14-pin plastic DIP and small, 16-pin QSOP packages in the commercial and extended temperature ranges.

MAX3100 Datasheet FAQs