LTC4307-1 Datasheet

• Bidirectional Buffer for Display Data Channel (DDC)
• Compliant with HDMI Specifi cation Version 1.3 DDC Capacitance Requirement
• Level Translation Between 3.3V and 5V
• ±5kV Human Body Model ESD Protection
• 60mV Buffer Offset Independent of Load
• Compatible with Non-Compliant VOL I²C Devices
• Isolates Input SDA and SCL Line from Output
• Compatible with I²C^™, I²C Fast Mode and SMBus
• READY Open-Drain Output
• High Impedance SDA, SCL Pins for V_CC = 0V
• Small 8-Lead (3mm × 3mm) DFN and 8-Lead MSOP Packages

• HDMI
• 3.3V/5V Level Translation
• Capacitance Buffer/Bus Extender

The LTC4307-1 is a 2-wire bus buffer that provides capacitance buffering between input and output. The HDMI specification requires that devices have less than 50pF of input capacitance on their DDC bus lines. The LTC4307-1’s capacitance buffering feature, in conjunction with its sub-10pF data and clock input capacitance, allows HDMI components to easily meet the 50pF requirement and tolerate high capacitance on the internal bus.

The LTC4307-1 also provides level-shifting between 3.3V and 5V systems to allow lower voltage HDMI transmitters, receivers and EEPROM to interface to the 5V DDC bus. READY is an open-drain digital output flag that indicates whether or not the input and output busses are connected and can interface to the HDMI hot plug detect (HPD) signal. When driven high, the ENABLE digital input allows the LTC4307-1 to connect after a stop bit or bus idle. Driving ENABLE low breaks the connection between the input and output busses.