LTC2230 Datasheet

• Sample Rate: 170Msps
• 61dB SNR up to 140MHz Input
• 75dB SFDR up to 200MHz Input
• 775MHz Full Power Bandwidth S/H
• Single 3.3V Supply
• Low Power Dissipation: 890mW/660mW
• LVDS, CMOS, or Demultiplexed CMOS Outputs
• Selectable Input Ranges: ±0.5V or ±1V
• No Missing Codes
• Optional Clock Duty Cycle Stabilizer
• Shutdown and Nap Modes
• Data Ready Output Clock
• Pin Compatible Family
  • 185Msps: LTC2220-1 (12-Bit)
  • 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)
  • 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)
• 64-Pin 9mm x 9mm QFN Package

• Wireless and Wired Broadband Communication
• Cable Head-End Systems
• Power Amplifier Linearization
• Communications Test Equipment

The LTC2230 are 170Msps, sampling 10-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2230 are perfect for demanding communications applications with AC performance that includes 61dB SNR and 75dB spurious free dynamic range for signals up to 200MHz. Ultralow jitter of 0.15ps_RMS allows undersampling of IF frequencies with excellent noise performance.

DC specs include ±0.2LSB INL (typ), ±0.1LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.12LSB_RMS.

The digital outputs can be either differential LVDS, or single-ended CMOS. There are three format options for the CMOS outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V.

The ENC⁺ and ENC^– inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.