LTC2224 Datasheet

• Sample Rate: 135Msps
• 67.3dB SNR up to 140MHz Input
• 80dB SFDR up to 150MHz Input
• 775MHz Full Power Bandwidth S/H
• Single 3.3V Supply
• Low Power Dissipation: 630mW
• CMOS Outputs
• Selectable Input Ranges: ±0.5V or ±1V
• No Missing Codes
• Optional Clock Duty Cycle Stabilizer
• Shutdown and Nap Modes
• Data Ready Output Clock
• Pin Compatible Family
  • 135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)
  • 105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)
  • 80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)
• 48-Pin 7mm × 7mm QFN Package

• Wireless and Wired Broadband Communication
• Cable Head-End Systems
• Power Amplifier Linearization
• Communications Test Equipment

The LTC2224 is a 135Msps, sampling 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2224 is perfect for demanding communications applications with AC performance that includes 67.3dB SNR and 80dB spurious free dynamic range for signals up to 150MHz. Ultralow jitter of 0.15ps_RMS allows undersampling of IF frequencies with excellent noise performance.

DC specs include ±0.4LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.5LSB_RMS.

A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V.

The ENC⁺ and ENC^– inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.