LTC2207 Datasheet

• Sample Rate: 105Msps
• 78.2dBFS Noise Floor
• 100dB SFDR
• SFDR >82dB at 250MHz (1.5V_P-P Input Range)
• PGA Front End (2.25V_P-P or 1.5V_P-P Input Range)
• 700MHz Full Power Bandwidth S/H
• Optional Internal Dither
• Optional Data Output Randomizer
• Single 3.3V Supply
• Power Dissipation: 900mW/725mW
• Optional Clock Duty Cycle Stabilizer
• Out-of-Range Indicator
• Pin Compatible Family
  • 105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit)
  • 80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit)
  • 65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit)
  • 40Msps: LTC2204 (16-Bit)
  • 25Msps: LTC2203 (16-Bit) Single-Ended Clock
  • 10Msps: LTC2202 (16-Bit) Single-Ended Clock
• 48-Pin 7mm × 7mm QFN Package

• Telecommunications
• Receivers
• Cellular Base Stations
• Spectrum Analysis
• Imaging Systems
• ATE

The LTC2207 are 105Msps, sampling 16-bit A/D converters designed for digitizing high frequency, wide dynamic range signals up to input frequencies of 700MHz. The input range of the ADC can be optimized with the PGA front end.

The LTC2207 are perfect for demanding communications applications, with AC performance that includes 78.2dB Noise Floor and 100dB spurious free dynamic range (SFDR). Ultralow jitter of 80fs_RMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include ±4LSB INL, ±1LSB DNL (no missing codes) over temperature.

A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V.

The ENC⁺ and ENC^– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles.