ADSP-2186N Datasheet

• 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle
• Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 200 CLKIN Cycle Recovery from Power-Down Condition
• Multifunction Instructions
• 12.5 ns Instruction Cycle Time @1.8 V (Internal), 80 MIPS Sustained Performance
• Single-Cycle Instruction Execution
• Single-Cycle Context Switch
• Low Power Dissipation in Idle Mode

The ADSP-2186N consists of six single chip microcomputers optimized for digital signal processing applications. All series members are pin-compatible and are differentiated solely by the amount of on-chip SRAM. This feature combined with ADSP-21xx code compatibility provide a great deal of flexibility in the design decision. Specifically, the series members are -

• ADSP-2186N (8K PM/8K DM) 

The ADSP-2186N offers the highest performance (80Mhz/MIPS) and lowest power consumption (0.55mW/MIP @ 1.8V) within the ADSP-218x portfolio. All series members are offered in a 100-lead LQFP and 144-Ball MBGA packages.