ADSP-21566 Datasheet

• 400MHz (max) Core clock frequency
• 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance
• 32-bit, 40-bit & 64-bit floating point support
• 32-bit fixed point
• Byte, short-word, word, long-word addressed

• 256KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases
• One Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices) SDRAM devices

• 1.35V support for DDR3L

• Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power
• Security Crypto Engines with OTP

• 8x Full SPORT interfaces w/TDM & I2S modes
• 2x S/PDIF Rx/Tx, 8 ASRC pairs
• 4x Precision Clock Generators
• 28 Buffers

• 2x Quad SPI, 1x Octal SPI
• MLB 3-pin
• 6x I2C,3x UARTs
• 2x Link Ports
• 10x General Purpose Timer, 1x General Purpose Counter
• 2x Watchdog Timers
• 4-ch 12bit Housekeeping ADCs
• 40 GPIO pins, 28 DAI pins
• Thermal Sensor

• 17mm x 17mm (0.8mm pitch) 400-ball CSP_BGA

• Security and Protection
  • Crypto hardware accelerators
  • Fast secure boot with IP protection
• Enhanced FIR and IIR accelerators running up to 1 GHz
• AEC-Q100 qualified for automotive applications

• Automotive:
  • audio amplifier, head unit, ANC/RNC, rear seat entertainment, digital cockpit, ADAS
• Consumer & Professional Audio:
  • speakers, sound bars, AVRs, conferencing systems, mixing consoles, microphone arrays, headphones

Reaching speeds of up to 1 GHz, the ADSP-21566 processors are members of the SHARC^® family of products. The ADSP-21566 processor is based on the SHARC+^® single core. The ADSP-21566 SHARC processors are members of the SIMD SHARC family of digital signal processors (DSPs) that feature Analog Devices, Inc., Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.

By integrating a rich set of industry-leading system peripherals and memory (see Table 1 in the data sheet), the SHARC+ processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.