ADRV9002 Datasheet

• 2 × 2 highly integrated transceiver
• Frequency range of 30 MHz to 6000 MHz
• Transmitter and receiver bandwidth from 12 kHz to 40 MHz
• Two fully integrated, fractional-N, RF synthesizers
• LVDS and CMOS synchronous serial data interface options
• Low power monitor and sleep modes
• Multichip synchronization capabilities
• Fast frequency hopping
• Dynamic profile switching for dynamic data rates and sample rates
• Fully integrated DPD for narrow-band and wideband waveforms
• Fully programmable via a 4-wire SPI
• 12 mm × 12 mm, 196-ball CSP_BGA

• Mission critical communications
• Very high frequency (VHF), ultrahigh frequency (UHF), and cellular to 6 GHz
• Time division duplexing (TDD) and frequency division duplexing (FDD) applications

The ADRV9002 is a highly integrated RF transceiver that has dual-channel transmitters, dual-channel receivers, integrated synthesizers, and digital signal processing functions.

The ADRV9002 is a high performance, highly linear, high dynamic range transceiver designed for performance vs. power consumption system optimization. The device is configurable and ideally suited to demanding, low power, portable and battery powered equipment. The ADRV9002 operates from 30 MHz to 6000 MHz and covers the UHF, VHF, industrial, scientific, and medical (ISM) bands, and cellular frequency bands in narrow-band (kHz) and wideband operation up to 40 MHz. The ADRV9002 is capable of both TDD and FDD operation.

The transceiver consists of direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, which eliminate the need for these functions in the digital baseband. In addition, several auxiliary functions, such as auxiliary analog-to-digital converters (ADCs), auxiliary digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs), are integrated to provide additional monitoring and control capability.

The fully integrated phase-locked loops (PLLs) provide high performance, low power, fractional-N frequency synthesis for the transmitter, receiver, and clock sections. Careful design and layout techniques provide the isolation required in high performance personal radio applications.

All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count. The local oscillators (LOs) have flexible configuration options and include fast lock modes.

The transceiver includes low power sleep and monitor modes to save power and extend the battery life of portable devices while monitoring communications.

The fully integrated, low power digital predistortion (DPD) is optimized for both narrow-band and wideband signals and enables linearization of high efficiency power amplifiers.

The ADRV9002 core can be powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard 4-wire serial port. Other voltage supplies are used to provide proper digital interface levels and to optimize the receiver, transmitter, and auxiliary converter performance.

High data rate and low data rate interfaces are supported using configurable CMOS or low voltage differential signaling (LVDS) serial synchronous interface (SSI) choice.

The ADRV9002 is packaged in a 12 mm × 12 mm, 196-ball chip scale package ball grid array (CSP_BGA).