ADF4382A Datasheet

• Fundamental output frequency range: 11.5 GHz to 21 GHz
• Divide by 2 output frequency range: 5.75 GHz to 10.5 GHz
• Divide by 4 output frequency range: 2.875 GHz to 5.25 GHz
• Integrated RMS jitter at 20 GHz = 20 fs (integration bandwidth: 100 Hz to 100 MHz)
• Integrated RMS jitter at 20 GHz = 31 fs (ADC SNR method)
• VCO autocalibration time < 100 μs
• Phase noise floor: −156 dBc/Hz at 20 GHz
• PLL specifications
  • −239 dBc/Hz: normalized in-band phase noise floor
  • −287 dBc/Hz: normalized 1/f phase noise floor
  • 625 MHz maximum phase/frequency detector input frequency
  • 4.5 GHz reference input frequency
  • Typical spurious f_PFD: −90 dBc
• Reference to output delay specifications
• Propagation delay temperature coefficient: 0.06 ps/°C
• Adjustment step size: <1 ps
• Multichip output phase alignment
• 3.3 V and 5 V power suppliesADIsimPLL^™ loop filter design tool support
• 7 mm × 7 mm, 48-terminal LGA
• −40°C to +105°C operating temperature

• High performance data converter clocking
• Wireless infrastructure (MC-GSM, 5G, 6G)
• Test and measurement

The ADF4382A is a high performance, ultralow jitter, fractional-N phased-locked loop (PLL) with an integrated voltage controlled oscillator (VCO) ideally suited for local oscillator (LO) generation for 5G applications or data converter clock applications. The high performance PLL has a figure of merit of −239 dBc/Hz, low 1/f noise and high PFD frequency of 625 MHz in integer mode that can achieve ultralow in-band noise and integrated jitter. The ADF4382A can generate frequencies in a fundamental octave range of 11.5 GHz to 21 GHz, thereby eliminating the need for subharmonic filters. The divide by 2 and divide by 4 output dividers on the ADF4382A allow frequencies to be generated from 5.75 GHz to 10.5 GHz and 2.875 GHz to 5.25 GHz, respectively.

For multiple data converter clock applications, the ADF4382A automatically aligns its output to the input reference edge by including the output divider in the PLL feedback loop. For applications that require deterministic delay or delay adjustment capability, a programmable reference to output delay with <1 ps resolution is provided. The reference to output delay matching across multiple devices and over temperature allows predictable and precise multichip clock and system reference (SYSREF) alignment.

The simplicity of the ADF4382A block diagram eases development time with a simplified serial peripheral interface (SPI) register map, repeatable multichip clock alignment, and limiting unwanted clock spurs by allowing off-chip SYSREF generation.