AD9642 Datasheet

• SNR = 71.0 dBFS at 185 MHz A_IN and 250 MSPS
• SFDR = 83 dBc at 185 MHz A_IN and 250 MSPS
• −152.0 dBFS/Hz input noise at 200 MHz, −1 dBFS A_IN, 250 MSPS
• Total power consumption:
  390 mW at 250 MSPS
• 1.8 V supply voltages
• LVDS (ANSI-644 levels) outputs
• Integer 1-to-8 input clock divider (625 MHz maximum input)
• Sample rates of up to 250 MSPS
• IF sampling frequencies of up to 350 MHz
• Internal ADC voltage reference
• Flexible analog input range 1.4 V_p-p to 2.0 V p-p (1.75 V_p-p nominal)
• See data sheet for additional features

• Communications
• Diversity radio systems
• Multimode digital receivers (3G)
• TD-SCDMA, WiMax, WCDMA,
  CDMA2000, GSM, EDGE, LTE
• I/Q demodulation systems
• Smart antenna systems
• General-purpose software radios
• Ultrasound equipment
• Broadband data applications

The AD9642 is a 14-bit analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9642 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired.

The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.

The ADC output data is routed directly to the external 14-bit LVDS output port.

Flexible power-down options allow significant power savings, when desired.

Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.

The AD9642 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.