AD9558 Datasheet

• Supports GR-1244 Stratum 3 stability in holdover mode
• Supports smooth reference switchover with virtually no disturbance on output phase
• Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems
• Supports ITU-T G.8262 synchronous Ethernet subordinate clocks
• Supports ITU-T G.823, G.824, G.825, and G.8261
• Auto/manual holdover and reference switchover
• 4 reference inputs (single-ended or differential)
• Input reference frequencies: 2 kHz to 1250 MHz
• Reference validation and frequency monitoring (1 ppm)
• Programmable input reference switchover priority
• 20-bit programmable input reference divider
• 6 pairs of clock output pins with each pair configurable as a single differential LVDS/HSTL output or as 2 single-ended CMOS outputs
• Output frequencies: 352 Hz to 1250 MHz
• Programmable 17-bit integer and 23-bit fractional feedback divider in digital PLL
• Programmable digital loop filter covering loop bandwidths from 0.1Hz to 5 kHz (2 kHz maximum for <0.1 dB of peaking)
• Low noise system clock multiplier
• Frame sync support
• Adaptive clocking
• Optional crystal resonator for system clock input
• On-chip EEPROM to store multiple power-up profiles
• Pin program function for easy frequency translation configuration
• Software controlled power-down
• 64-lead, 9 mm × 9 mm, LFCSP package

• Network synchronization, including synchronous Ethernet and SDH to OTN mapping/demapping
• Cleanup of reference clock jitter
• SONET/SDH/OTN clocks up to 100 Gbps, including FEC
• Stratum 3 holdover, jitter cleanup, and phase transient control
• Wireless base station controllers
• Cable infrastructure
• Data communications

The AD9558 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (OTN/SONET/SDH). The AD9558 generates an output clock synchronized to up to four external input references. The digital phase-locked loop (PLL) allows reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9558 continuously generates a low jitter output clock even when all reference inputs have failed.

The AD9558 operates over an industrial temperature range of −40°C to +85°C. If a smaller package is required, refer to the AD9557 for the two-input/two-output version of the same device.