AD9266-EP Datasheet

• 1.8 V analog supply operation
• 1.8 V to 3.3 V output supply
• SNR
  • 77.6 dBFS at 9.7 MHz input
  • 76.4 dBFS at 70 MHz input
• SFDR
  • 94 dBc at 9.7 MHz input
  • 93 dBc at 70 MHz input
• Low power
  • 111 mW at 65 MSPS
• Differential input with 700 MHz bandwidth
• On-chip voltage reference and sample-and-hold circuit
• 2 V p-p differential analog input
• DNL = −0.5/+1.0 LSB
• Interleaved data output for reduced pin-count interface
• Serial port control options
  • Offset binary, Gray code, or twos complement data format
  • Optional clock duty cycle stabilizer
  • Integer 1 to 8 input clock divider
  • Built-in selectable digital test pattern generation
  • Energy-saving power-down modes
  • Data clock output (DCO) with programmable clock and data alignment

• Supports defense and aerospace applications (AQEC standard)
• Military temperature range (−55°C to +125°C)
• Controlled manufacturing baseline
• Enhanced product change notification
• Qualification data available on request

• Communications
• Diversity radio systems
• Multimode digital receivers
  • GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
• Smart antenna systems
• Battery-powered instruments
• Handheld scope meters
• Portable medical imaging
• Ultrasound
• Radar/LIDAR
• PET/SPECT imaging

The AD9266-EP is a monolithic, single-channel 1.8 V supply, 16-bit, 65 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.

The product uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 65 MSPS data rates and to guarantee no missing codes over the full operating temperature range.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). 

A differential clock input with a selectable internal 1-to-8 divide ratio controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.

The interleaved digital output data is presented in offset binary, gray code, or twos complement format. A data clock output (DCO) is provided to ensure proper latch timing with receiving logic. CMOS levels from 1.8 V through 3.3 V are supported.

The AD9266-EP is available in a 32-lead RoHS compliant LFCSP and is specified over the −55°C to +125°C temperature range.

Additional application and technical information can be found in the AD9266 data sheet.