AD9266 Datasheet

16-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter

Part No.:
AD9266
Manufacturer:
Analog Devices, Inc.
Page:
32 Pages
Size:
1012 KB
Views:
0
Update Time:
2026-01-30 14:52:37

AD9266 DataSheet Applicable Part

Part No. In Stock Price Packaging SPQ Marking MSL Pins Temp Range Package Description
SPQ:Standard Pack Quantity;MSL:Moisture Sensitivity Level

AD9266 DataSheet PDF

AD9266 Features

  • 1.8 V analog supply operation
  • 1.8 V to 3.3 V output supply
  • SNR
    • 77.6 dBFS at 9.7 MHz input
    • 71.1 dBFS at 200 MHz input
  • SFDR
    • 93 dBc at 9.7 MHz input
    • 80 dBc at 200 MHz input
  • Low power
    • 56 mW at 20 MSPS
    • 113 mW at 80 MSPS
  • Differential input with 700 MHz bandwidth
  • See data sheet for additional features

AD9266 Applications

  • Communications
  • Diversity radio systems
  • Multimode digital receivers
    GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
  • Smart antenna systems
  • Battery-powered instruments
  • Handheld scope meters
  • Portable medical imaging
  • Ultrasound
  • Radar/LIDAR
  • PET/SPECT imaging

AD9266 Description

The AD9266 is a monolithic, single-channel 1.8 V supply, 16-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.

The product uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).

A differential clock input with a selectable internal 1-to-8 divide ratio controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.

The interleaved digital output data is presented in offset binary, gray code, or twos complement format. A DCO is provided to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported.

The AD9266 is available in a 32-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).

Product Highlights

  1. The AD9266 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.
  2. The sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.
  3. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO and data output (D15_D14 to D1_D0) timing and offset adjustments, and voltage reference modes.
  4. The AD9266 is packaged in a 32-lead RoHS-compliant LFCSP that is pin compatible with the AD9609 10-bit ADC, the AD9629 12-bit ADC, and the AD9649 14-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 80 MSPS.

AD9266 Datasheet FAQs