AD9211 Datasheet

• SNR = 60.1 dBFS @ f_IN up to 70 MHz @ 
  300 MSPS
• ENOB of 9.7 @ f_IN up to 70 MHz @ 300 MSPS (−1.0 dBFS)
• SFDR = −80 dBc @ f_IN up to 70 MHz @ 300 MSPS (−1.0 dBFS)
• Excellent linearity 
  DNL = ±0.1 LSB typical 
  INL = ±0.2 LSB typical
• LVDS at 300 MSPS (ANSI-644 levels)
• 700 MHz full power analog bandwidth
• On-chip reference, no external decoupling required
• Integrated input buffer and track-and-hold
• Low power dissipation 
  437 mW @ 300 MSPS—LVDS SDR mode
  410 mW @ 300 MSPS—LVDS DDR mode
• Programmable input voltage range 
  1.0 V to 1.5 V, 1.25 V nominal
• 1.8 V analog and digital supply operation
• Selectable output data format (offset binary, twos complement, Gray code)

• Wireless and wired broadband communications
• Cable reverse path
• Communications test equipment
• Radar and satellite subsystems
• Power amplifier linearization

The AD9211 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 300 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution.

The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.

Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead LFCSP, specified over the industrial temperature range (−40°C to +85°C).