AD4004 Datasheet

• Easy Drive expands signal chain flexibility
  • High-Z mode significantly reduces signal chain settling requirements
  • Fast conversion phase extends the ADC acquisition time
  • Input overvoltage protection clamp sinks up to 50 mA
• High performance
  • First conversion accurate, no latency or pipeline delay
  • Guaranteed 16-bit, no missing codes
  • Throughput: 2 MSPS/1 MSPS/500 kSPS options
  • INL: ±1.0 LSB maximum
  • SNR: 93 dB at f_IN = 1 kHz, VREF = 5 V
  • THD: −115 dB at f_IN = 1 kHz; −95 dB at f_IN = 100 kHz
  • Pseudo differential input range
  • Flexible external reference voltage range (2.4 V to 5.1 V)
• Low power
  • Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
  • 2.5 mW at 500 kSPS (VDD only)
  • 70 μW at 10 kSPS, 14 mW typical at 2 MSPS (total power)
• SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface
• 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP
• Guaranteed operation: −40°C to +125°C

• Automated test equipment
• Machine automation
• Medical equipment
• Battery-powered equipment
• Precision data acquisition systems
• Instrumentation and control systems

The AD4004 are high accuracy, high speed, low power, 16-bit, precision successive approximation register (SAR) analog-to-digital converters (ADCs). These ADCs incorporate Easy Drive features, such as high-Z mode and an extended acquisition phase, which provide signal chain architectural flexibility by expanding the range of companion circuitry that can be paired with these ADCs.

Operating from a single power supply, VDD, these ADCs allow the reference voltage, V_REF, to be applied externally and set independently of the supply voltage. With fast device throughput up to 2 MSPS, the AD4004 can accurately capture high-frequency signals and implement oversampling techniques to alleviate the challenges associated with antialias filter designs. Additionally, the power consumption of these ADCs scales linearly with throughput.

The AD4004 eliminate the need for a negative supply to the ADC driver amplifier by employing input span compression, while preserving access to the full ADC code range. Furthermore, the input overvoltage clamp protects the ADC inputs against overvoltage events, minimizing disturbances on the reference pin and eliminating the need for external protection diodes.

By reducing the serial peripheral interface (SPI) clock rate requirements, the AD4004 reduce digital input and output power consumption, broaden digital host options, and simplify the task of sending data across digital isolation. The SPI-compatible serial user interface supports 1.8 V, 2.5 V, 3.3 V, and 5 V logic by using the separate VIO logic supply.